1. Field of the Invention
The present invention relates generally to multi-data rate memories, such as double-data rate (DDR) memories and, more particularly, to the ordering of multiple data retrieved during a dual or multi-data rate read operation.
2. State of the Art
Data intensive applications for computers, such as personal computers, are becoming increasingly more popular. Such data intensive applications include graphics-intensive applications, including real-time imaging, games, animation and others. As these applications become more complex, they require hardware platforms (e.g., computers) on which they execute to improve in performance and capability. In an attempt to accommodate such data-intensive applications, microprocessors within computers have become increasingly faster in their performance. However, microprocessors require accessible data from memory upon which to operate and present for such applications.
One approach for making data more readily available to a microprocessor has been the development of multi-data rate memory, namely a double-data rate (DDR) memory. DDR memory is named from is functional characteristic of using the rising and falling edge of the memory bus clock for timing. Whereas traditional memory modules use only the rising edge of the clock for timing, DDR memory can effectively double the data rate of data that is available to a microprocessor by making a first retrieved word of data available on the rising edge of the memory bus clock and a second retrieved word of data available on the falling edge of the memory bus clock. Such an implementation improves the overall bandwidth of a memory as seen by the microprocessor.
A DDR memory typically operates by simultaneously retrieving two words of data, each word of n-bits in length with one word from an even memory cell bank and the other word from an odd memory cell bank, with both words from the same location within the memory as addressed by the logical circuitry. While two separate words are retrieved in parallel, they are ordered for individual sequential outputting to the microprocessor. The ordering of the two separate words is also unique to various programming applications. For example, one application programming technique may be configured to perform an incrementing access of sequentially stored data elements with incrementing data stored first in the even memory location followed by the next data being stored in the odd memory location. Conversely, another programming technique may perform a different process on data by retrieving the data from the DDR memory and requesting the output ordering of the retrieved words of data to begin with odd memory location or requesting the odd bank data word being output first followed by the even memory location or even bank data word. Maintaining the desired ordering of the present words is crucial for accurate data manipulation and presentation.
Another approach for improving the bandwidth of memories includes pipelining of memory read operations. Reading of data from a memory device typically requires more than a single processor clock cycle in order to (i) address the specific memory location, (ii) sense the data at that location and (iii) output the sensed data. This delay is typically referred to as “read latency.” Specifically, read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. In order to improve the bandwidth of memory devices, one or more subsequent read commands can be issued before the end of a previous read operation's latency period.
The issuance of overlapping read operations in a single data rate memory results in consecutive outputting of each of the individually retrieved words. However, in a multi-data rate memory, such as a DDR memory, where multiple overlapping read operations each yield multiple words of data, tracking the ordering of the outputting of the data word pairs with the corresponding read operation becomes problematic. Additionally, since each read operation in DDR memory specifies a specific ordering of the retrieved words when output to the microprocessor, data errors may occur if the read operation specifics (i.e., ordering of word pairs) do not remain matched with the outputting process from the memory.
There is a need, therefore, for reliably ordering data retrieved from a multi-data rate read operation as specified in the initial read command. For these and other reasons, there is a need for the present invention.